EIC TECH SYS
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🎓 Training completion certification based on request
Course Duration
15 Weeks
Schedule
2 Days / Week
Timings
21:30 to 23:30
Fee Structure
10K (Payable in 2 installments)
Course Structure Overview
Module 1:
Altium Workspace & Data Management
Workspace Setup:
Configure Altium Designer access.
Version Control:
Implement and create standardized project templates.
Lifecycle Management:
Define component states (Draft, Production) and revision workflows.
Data Exchange:
Introduce IPC-2581 basics for manufacturing handoff.
Module 2:
Advanced Symbol & Footprint Creation
IPC-7351C Compliance:
Calculate footprint fillets for Density Levels A, B, and C.
3D Integration:
Automate footprint generation and align STEP models for mechanical checks.
Padstack Design:
Configure thermal reliefs and precise paste mask expansions.
BGA Strategies:
Create multi-part symbols and manage pin mapping for high-pin-count ICs.
Module 3:
Impedance Layer Stack Up Configuration
Material Selection:
Choose dielectrics based on IPC-4101 parameters (Tg, Dk, Df).
Stack-Up Construction:
Build symmetrical core/prepreg structures up to 16+ layers.
Impedance Profiling:
Calculate 50Ω single-ended and 90Ω/100Ω differential profiles.
Documentation:
Generate stack-up tables and impedance fabrication notes.
Module 4:
Crosstalk Mitigation Techniques
Crosstalk Analysis:
Mitigate Near-End (NEXT) and Far-End (FEXT) coupling.
Constraint Manager:
Program advanced clearance matrices and the "3W/5W Rule."
Isolation Routing:
Apply orthogonal routing, guard traces, and via stitching.
Differential Pairs:
Execute static and dynamic phase tuning and length matching.
Module 5:
Power Supply Layout Guidelines
Current Capacity:
Calculate trace widths and temperature rise strictly using IPC-2152.
PDN Optimization:
Place high-frequency decoupling capacitors to minimize loop inductance.
Plane Management:
Design overlapping polygons and manage solid return paths.
Thermal Design:
Implement thermal via arrays under exposed pads and regulators.
Module 6:
Final Microcontroller Project Integration
Placement & Floorplanning:
Isolate high-speed digital interfaces from analog/power zones.
I2C & SPI Routing:
Manage bus capacitance, pull-ups, and series termination resistors.
USB Routing:
Enforce 90Ω differential rules, tight length matching, and ESD placement.
DFM Checks:
Run comprehensive Design Rule Checks against IPC Class 2/Class 3.
Manufacturing Files:
Automate OutJob generation for IPC-2581/Gerbers, BOMs, and Assembly Drawings.
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